Standard Protocol for De-Embedding S-Parameter Calibration Data on Test Benches
Stripping test fixture phase delay and magnitude loss from raw vector network analyzer measurements ensures true S-parameter extraction.
Launch Parasitics
Meaning
Localized capacitive and inductive discontinuities at the transition between a connector pin and a printed circuit board degrade high frequency signals. In high speed rf boards, launch parasitics occur when a trace encounters the solder pad of a coaxial connector.
Impedance Mismatch
Large solder pads on thin outer layers create excess capacitance that drops the characteristic impedance of the transmission line below fifty ohms, creating a mismatch that reflects signal energy back to the transceiver. This impedance dip reflects signal energy back to the transceiver, increasing the return loss of the channel. The signal suffers from attenuation and phase distortion before it reaches the transmission medium, limiting the maximum bandwidth of the product.
Discontinuity Effect
High frequency components of a digital signal travel through transitions with different delays when parasitic elements are uncompensated. The resulting distortion closes the receiver eye diagram, raising the bit error rate of the channel. At millimetre-wave bands, these parasitic elements can completely block signal transmission by acting as a low-pass filter.
Layout Compensation
Layout designers mitigate these effects by removing internal ground plane copper beneath the pad to reduce capacitance. Adding stitching vias around the transition provides a short return path for the high frequency current, which balances the local inductance. These adjustments are tested using electromagnetic simulation tools before the final board is fabricated.