Meaning
Logical models used in digital circuit testing simulate the behavior of physical defects by fixing a signal line to a permanent high or low voltage level. Applying a stuck-at fault to a net allows test engineers to evaluate the effectiveness of test patterns in detecting manufacturing defects. This abstraction represents the industry standard for evaluating digital circuit test coverage.
Diagnostic Model
The model categorizes faults into two states, stuck-at-zero and stuck-at-one. Physical shorts to ground or power lines exhibit this behavior. Modeling these errors allows automatic test pattern generators to calculate the exact vectors needed to expose them.
Test Coverage
Grading the quality of a test program involves simulating how many of these potential failures are detected by the vector set. A higher percentage of detected faults corresponds to a lower probability of shipping defective components. Calculating this ratio allows the design team to identify untested nodes and write additional vectors to cover them.
Verification Execution
Running these tests on the manufacturing floor involves applying the generated digital patterns to the inputs of the device and comparing the output pins against expected values. Discrepancies between the expected and measured responses indicate the presence of a physical defect. This automated routine completes in milliseconds, providing rapid go-no-go decisions during chip packaging and board-level assembly to maintain throughput.
