AHB-Lite Bus

Bus Topology

A central multiplexer routes address, control, and write data signals to the selected peripheral. System designers connect the ahb-lite bus in a hierarchical configuration where the master has exclusive control over the transaction initiation. Slaves receive the address phase signals directly and respond during the subsequent data phase.

This separation of address and data phases allows pipelined operation.

Protocol Transfer

Transactions require a minimum of two clock cycles, starting with the address phase and ending with the data phase. During the first cycle, the ahb-lite bus driving master outputs the address and control signals to indicate the transfer size, direction, and burst type. The active peripheral then evaluates these signals.

In the second cycle, the slave completes the data transfer by driving the response and read data signals. If the peripheral requires more time to process the data, it inserts wait states by pulling the ready signal low to stall the master. This simple mechanism prevents data loss without complex handshaking protocols.

System Interface

Interface signals include clock, reset, and transfer status indicators. For a successful integration, the ahb-lite bus demands that all connected modules synchronize to the same rising edge of the system clock. System engineers evaluate the bus performance during the static timing analysis phase to ensure zero clock skew issues.

This verification ensures that no timing violations compromise the integrated system-on-chip.