Meaning
Percentage of potential manufacturing defects detected by a specific set of test patterns determines the risk of shipping a faulty integrated circuit. High fault coverage is achieved by running simulation tools that inject simulated faults into the gate-level netlist of the design. It measures how effectively the test program exercises the internal nodes of the silicon.
Achieving a high percentage is necessary to prevent defective chips from passing the wafer sort phase.
Test Execution
Automation tools generate specific input patterns that are applied to the device under test by automatic test equipment. These vectors drive the internal flip-flops into known states and observe the resulting outputs for anomalies. If a node is stuck at a high or low voltage, the test pattern must force that node to the opposite state to expose the defect.
Coverage Metric
Developers use scan chains embedded within the design to access deep logic blocks that are not directly connected to the package pins. This internal access allows the test software to increase the detection rate of potential manufacturing defects. The final percentage is reported to the system integrator as part of the production release package.
Quality Correlation
Low detection rates in the test suite lead to a higher rate of defective parts arriving at the customer assembly line. While increasing the test density requires more test time on expensive equipment, it reduces the costs associated with board-level troubleshooting and field returns. Optimizing this parameter involves balancing test costs against the target return rate.
