Meaning
Dual-bank memory architecture allows a microcontroller to alternate the logical mapping of its physical flash memory regions. This configuration enables the system to execute application code from one bank while simultaneously writing a new firmware image to the second bank. Once the write operation is complete, the processor changes the internal mapping so that the next reboot executes from the updated bank.
Hardware Execution
The memory controller manages the address redirection internally without requiring the application code to be compiled for different execution addresses. This eliminates the need for complex position-independent code or identical binaries built for different memory offsets. The physical bank designated as bank zero is mapped to the reset address during the swap.
Update Sequence
The application receives the update payload and writes it directly to the inactive bank. Once the transfer is complete and the integrity check succeeds, the configuration register is updated to execute the bank swap on the next system reset. This approach reduces update downtime to a simple processor reset.
System Recovery
The bootloader retains the option to revert the bank swap if the new application fails to boot. If the startup self-test fails, the bootloader toggles the swap configuration back to the original state. This mechanism provides a robust fallback path that maintains device availability.