Managing Silicon Errata Workarounds in Transferred Firmware Repositories
Managing errata workarounds in transferred firmware requires isolating stepping-specific register fixes to prevent fatal regressions across new silicon wafer lots.
Wait States
Meaning
Processor execution cycles are sometimes delayed by the insertion of idle clock periods when accessing slower memory or peripheral devices. These delays, known as wait states, are generated by the bus controller when a fast processor reads from or writes to a slow hardware resource. They ensure that the data remains stable on the bus long enough for the slower device to complete the transaction without errors.
The application of wait states is confined to external bus cycles and does not affect the internal execution of instructions within the processor core itself.
Memory Access
Read and write cycles are stretched by the memory controller to accommodate the timing specifications of external flash or RAM. When using wait states, the hardware delays the acknowledgment signal until the data lines are stable. This technique allows cheap, slower memory to be used with fast microcontrollers.
Processor Stall
Instruction queues stall when the processor enters a suspended state, halting code execution until the wait cycle finishes. This state prevents the execution of subsequent instructions that depend on the incoming data.
Performance Penalty
System designers minimize these delays by using cache memory or configuring the direct memory access controller. Stalling the processor reduces the effective clock speed of the system.