Trap Rich Polysilicon Layer Optimization for Harmonic Suppression in Front End Modules
Trap rich polysilicon layers freeze interface charges to hold high resistivity and suppress switch harmonics below minus eighty dBc.
C-V Profiling
Meaning
Analytical measurement of semiconductor capacitance as a function of an applied direct-current bias voltage determines the carrier concentration as a function of depth. Executing C-V profiling reveals the spatial distribution of dopants and the density of interface states within a device structure. The technique assumes a one-dimensional depletion approximation and becomes inaccurate when the test structure is extremely thin or highly conductive, because leakage currents can dominate the measured admittance.
Dopant Distribution
Varying the bias voltage changes the depletion layer width within the semiconductor material. Measuring the change in capacitance per unit voltage step allows calculation of the local carrier density. This provides a direct measure of the active dopant profile without destroying the wafer.
Interface Evaluation
Inversion and depletion regimes during the measurement cycle reveal the presence of trapped charges. Frequency-dependent measurements distinguish between fast and slow interface states at the dielectric boundary. This helps qualify the passivation quality of gate oxides.
Hardware Measurement
Automated probe stations use high-precision LCR meters to record the capacitance at high frequencies. Test structures must be designed with sufficient area to provide signal levels above the noise floor of the instrument. Shielded cabling is required to minimize parasitic inductance and capacitance during the scan.