Trap retention in RF-SOI substrates degrades above 1000 C through grain coarsening, requiring millisecond anneals to preserve resistivity and harmonic suppression.
Trap-rich polysilicon layers beneath buried oxide pin interface carriers to eliminate parasitic conduction and lower sub-6 GHz harmonic generation.
Trap-rich polysilicon layers suppress parasitic surface conduction in high-resistivity silicon transceivers, lowering second harmonics below -85 dBc at +25 dBm RF input.
Trap rich polysilicon layers freeze interface charges to hold high resistivity and suppress switch harmonics below minus eighty dBc.
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