Meaning
Hardware debugging in complex multi-core microprocessors requires specialized data collectors to gather diagnostic output from multiple on-chip sources. A coresight trace funnel combines multiple trace streams from different processor cores or hardware blocks into a single output stream. This routing tool allows developers to monitor multiple diagnostic sources simultaneously using fewer physical output pins on the device package.
Stream Consolidation
Debug architectures must serialize parallel flows of trace information to prevent channel clutter. The coresight trace funnel acts by prioritizing and interleaving data packets from active trace sources according to hardware control registers. This consolidation preserves the timing relationships between events on different cores.
System designers configure the priority of each input port to prevent data from a high-frequency source from overwriting information from slower blocks.
Bandwidth Constraint
Data losses occur when the aggregate input trace rate exceeds the capacity of the output channel. This bottleneck occurs because a coresight trace funnel cannot compress the trace packets that pass through it. If the trace data rate is too high, the internal buffers will overflow and drop diagnostic packets.
System Integration
Board designers must route trace signals to external debug connectors using high-speed layout rules to maintain signal fidelity. When integrating a coresight trace funnel into a system-on-chip design, designers use control interfaces to dynamically enable or disable specific trace sources during software testing. This configuration capability prevents trace buffer overflows by limiting diagnostic collection to the modules under test.
Field application engineers utilize automated scripts during board bring-up to verify that trace output matches known-good test patterns.
