Meaning
Memory bus communication latency events occur when a master device must wait for a memory controller to fulfill a read request. In high-performance architectures, split-transaction stalls happen when the split-transaction bus has depleted its tracking resources and cannot accept new requests until outstanding ones are completed. This mechanism decouple the request from the response, allowing other devices to use the bus in the interim.
A stall occurs only when the limits of this decoupling are reached.
Resource Limitation
Internal tracking queues or outstanding transaction buffers have a finite capacity. When multiple masters issue read requests simultaneously, the memory controller fills its queues quickly. If those queues become full, the bus controller must refuse further requests.
This state halts progress on the initiating master until the controller returns the oldest requested data.
System Consequence
Processor cores can experience stalled pipelines when instruction or data fetches are delayed by these stalls. This delay degrades overall system throughput and can cause real-time tasks to miss their deadlines. Engineers must analyze these bus bottlenecks using simulation tools.
These stalls represent a limiting factor in overall processor efficiency.
Design Mitigation
Increasing queue depths or utilizing out-of-order execution logic help mitigate the frequency of these transaction stalls. Designers can also optimize compiler behavior to reduce back-to-back memory access commands. This reduces unnecessary bus traffic.
