Microcontroller Bootloader Architecture and Dual Bank Flash Partitioning
Dual-bank flash partitioning enables fail-safe firmware updates by isolating execution to Bank A while writing and verifying new images on Bank B before reset.
Cortex-M VTOR
Meaning
Vector table offset register configuration determines the memory address where the processor locates the initial stack pointer and interrupt service routines. This register allows the microcontroller to dynamically change the exception vector address during runtime or boot. By adjusting the register value, the system directs the processor to run code from different physical regions of memory such as a bootloader or a newly updated application image.
Memory Alignment
The base address configured in the register requires strict boundary alignment to ensure proper execution. Hardware architectures typically demand that the address is aligned to a power of two based on the number of supported interrupts. Misalignment results in undefined behavior or a hard fault immediately upon the first exception.
Boot Sequence
At reset, the processor defaults to reading the initial vector table from address zero. The system bootloader initiates and configures the peripheral controllers, then modifies the register to point to the starting address of the validated application. This transition transfers control to the new execution context cleanly.
Runtime Application
System firmware utilizes runtime modification of the register to manage complex interrupt handling. When the device executes from flash memory but needs to run time-critical interrupt routines from random access memory, the register is updated to point to the ram copy. This action reduces interrupt latency by avoiding flash wait states.