Microcontroller Bootloader Architecture and Dual Bank Flash Partitioning
Dual-bank flash partitioning enables fail-safe firmware updates by isolating execution to Bank A while writing and verifying new images on Bank B before reset.
Flash Page Erase
Meaning
Fundamental memory management operation that resets a specific block of non-volatile cells to a logic high state. A flash page erase is required before any new data can be written to a previously occupied memory address. This process differs from byte level access because it affects an entire structural unit of the storage array.
Operational Command
Control signal sent to the memory controller initiates the voltage discharge required to clear the bits. Performing a flash page erase involves setting the target address and waiting for the internal charge pump to complete the task. The hardware remains busy during this period and cannot process read requests.
Wait State
Temporal delay occurs while the physical charges are removed from the floating gates. The duration of a flash page erase depends on the specific architecture of the silicon, often ranging from several milliseconds to much longer periods. System software must poll a status register or wait for an interrupt to signal completion.
Cell Endurance
Physical limitation restricts the total number of times a block can be cleared. Repeated execution of a flash page erase causes gradual wear on the oxide layer of the transistor. Wear leveling algorithms distribute these operations across the entire memory array to prevent premature failure of the storage module.
This management is essential in systems that frequently log data or store telemetry. High endurance memory parts may support many thousands of cycles before the bit integrity degrades.