Meaning
Equivalence validation processes compare two representations of a digital design to confirm that they exhibit identical logical behavior. Implementing logic equivalence checking verifies that steps such as synthesis, optimization, or manual netlist edits have not changed the functionality of the system. This check does not use test vectors, operating instead by comparing mathematical representations of the logic.
Formal Comparison
Verification engines convert both the register-transfer level code and the post-synthesis netlist into binary decision diagrams. The tool then compares these structures at defined boundaries such as registers and output pins. If a discrepancy exists, the tool outputs a counterexample trace that shows the mismatch.
Comparing the designs mathematically avoids the long runtimes of dynamic simulations.
Structural Boundary
Partitioning the design into smaller, independent logic blocks allows the engine to handle millions of gates. Each block has a start point and an end point where the comparison takes place. These points are typically flip-flops or top-level output pads.
Proper boundary alignment prevents false mismatch alerts during the verification run.
Post Synthesis
Circuit modifications such as clock tree insertion or scan chain insertion are verified to ensure that the original function remains intact. Netlist changes made during these layout steps must be checked before proceeding to tape-out. Equivalence tools quickly run these checks after each major layout iteration.
Using formal checking ensures that no logical errors are introduced during physical design.
