Meaning
Fault tolerance verification is a test method where a processor reset is forced by deliberately disabling or delaying the refresh signal to a supervisory timer. Watchdog reset injection verifies that the system firmware and hardware can safely recover from a software lockup or unexpected crash. It proves the effectiveness of the fallback recovery mechanisms.
Fault Simulation
Automated test scripts intercept the normal timer service routine or force the processor into an infinite loop to prevent the watchdog service command from executing. Once the timer interval expires without receiving the required refresh signal, the supervisor triggers a hardware reset. This action replicates the behavior of a system that has hung due to a resource deadlock or memory leak.
Recovery Sequence
After the reset occurs, the startup code must inspect the internal reset status register to identify the source of the reboot. If the reset was triggered by the supervisor, the bootloader skips the normal user-interactive pause and executes a rapid recovery sequence to restore critical services. The application must then read its last saved state from non-volatile storage to resume operation from where it was interrupted.
This sequence must execute within a strict time limit to prevent long service interruptions in critical communications hardware.
Validation Method
Engineers run this test repeatedly during automated testing to confirm that the hardware starts up in a predictable and safe configuration. The monitoring software verifies that the system registers are correctly cleared and that the logs record the reset event. A successful test run shows that the device did not enter a permanent boot loop.