Meaning
Parasitic values representing the unintended inductive property of the fine wires used to connect an integrated circuit die to its package leadframe define the electrical impedance of the interconnect. The wirebond parasitic inductance limits the high-frequency performance of the packaged device and contributes to signal degradation and power rail noise. Minimizing this value is a major objective in high-speed packaging design.
Physical Geometry
Inductance is determined by the length, diameter, and height of the bond wire loop. Longer wires create larger current loops, which increases the inductive value. Designers reduce this value by keeping the bond wires as short and straight as possible.
Using multiple parallel wires for power and ground connections also helps by dividing the inductance.
Signal Degradation
High inductance on signal lines creates a low-pass filter when combined with the pin and trace capacitance. This filter attenuates the high-frequency components of the signal, slowing down the transition times. The inductance also causes signal reflections due to the impedance mismatch between the die pad and the board trace.
High-frequency devices use ball grid array packaging to bypass bond wires entirely.
Package Noise
Transitioning currents flowing through the return path wires induce transient voltages on the ground connection of the die. This ground bounce can cause logical errors in the input buffers of the chip. Placing ground bonds next to signal bonds helps by providing a close return path, reducing the loop area.
Packaged designs must minimize this inductance to maintain signal and power integrity.
