Meaning
Data files written in the boundary scan description language enable automated test equipment to interact with the internal logic of complex integrated circuits. Each bsdl model provides a machine-readable description of how the JTAG architecture is implemented in a specific component. It maps the internal boundary scan cells to the physical pins of the package.
Boundary Scan
Testing of modern circuit boards relies on the ability to shift data through shift registers located at the device pins. The bsdl model defines the length and structure of these registers. Without this information, a tester cannot determine which bit in the serial stream corresponds to a specific net on the board.
File Verification
Accuracy in the description of the instruction register and boundary cells prevents damage during boundary scan operations. A faulty bsdl model might cause the tester to attempt to drive an input-only pin or create a contention on the bus. Engineers often verify these files against the physical silicon before starting production.
Integration Utility
Synthesis tools use these descriptions to generate test patterns for detecting solder bridges and open circuits. A bsdl model facilitates the automation of inter-chip interconnect testing. This file provides the primary interface between the semiconductor manufacturer and the board-level test engineer.
