Trap Rich Polysilicon Layer Optimization for Harmonic Suppression in Front End Modules
Trap rich polysilicon layers freeze interface charges to hold high resistivity and suppress switch harmonics below minus eighty dBc.
Dynamic Capacitance
Meaning
Voltage-dependent and time-varying capacitive response of a semiconductor junction occurs under alternating-current excitation or transient bias sweeps. The evaluation of dynamic capacitance reveals the charge-discharge behavior of deep-level traps and surface states that do not respond to static voltages. This phenomenon is bounded by the transit time of carriers across the depletion region and the measurement frequency, which determines the maximum speed at which the traps can exchange carriers with the bands.
Transient Response
Rapid voltage transitions force carriers to enter or leave localized trap states at different rates. This asymmetry leads to a hysteresis in the measured capacitance during upward and downward sweeps. Analysing this lag provides details on the energy distribution of the defects.
Distortion Effect
Non-linear capacitive behavior under high-frequency signals generates unwanted harmonic components. This dynamic variation in capacitance degrades the linearity of radio-frequency switches and power amplifiers. Designers must model this effect to predict intermodulation distortion in transceivers.
Analytical Method
High-frequency impedance analysers record the phase and amplitude of the displacement current under a superimposed sweep voltage. Sweeping the frequency of the test signal separates the fast interface states from the slow bulk traps. This profiling is essential for optimizing the dielectric interfaces of power devices.