Meaning
Electrical contact verification relies on micro-probe testing to measure sub-micron signal paths on semiconductor dice before packaging. Physical manipulation of tungsten tips onto microscopic bond pads establishes immediate continuity without damaging adjacent passivation layers. Production engineers apply this diagnostic procedure during wafer fabrication to isolate manufacturing defects prior to final assembly.
Probe Alignment
Mechanical positioning requires sub-micron accuracy to prevent catastrophic damage to delicate aluminum structures beneath the probe tip. Thermal expansion introduces dimensional shifts across the test stage, necessitating active calibration routines between touchdown cycles. Engineers monitor scrub marks left by the descending tungsten needle to confirm proper over-travel and contact resistance values.
Contact Resistance
Current injection through microscopic interfaces generates localized heating that alters measured resistance if voltage drops exceed threshold limits. Oxidation films on aluminum pads create high-impedance barriers that standard DC measurements fail to penetrate without adequate overdrive force. Operator calibration logs record baseline resistance profiles to separate probe tip degradation from genuine silicon anomalies.
Yield Loss
Defect mapping transforms raw voltage signatures into spatial distribution charts that highlight systematic lithography failures across the entire wafer surface. Factory supervisors review these defect classifications during final electrical test handovers to determine scrap percentages before packaging commitments. Automated sorting algorithms isolate marginal devices to protect downstream board assembly lines from premature component failure.
