Silicon Substrate Surface Conduction and Dielectric Passivation Fundamentals
Trap-rich polysilicon passivation pins interface charges on high-resistivity silicon, suppressing surface conduction and harmonic spur spikes across RF switches.
Mid Gap Trap Pinning
Meaning
The immobilization of the Fermi level near the center of a semiconductor band gap occurs when a high density of surface states exists. In radio frequency transistors, mid gap trap pinning prevents the gate voltage from effectively modulating the conduction channel. This phenomenon reduces the maximum drain current and limits the switching speed of the device.
Defect Origin
Unsatisfied chemical bonds at the boundary between the semiconductor and the passivation layer create these localized energy states. Chemical residues from etching processes or thermal stress during deposition can also generate these defects. Once mid gap trap pinning is established, the transistor exhibits a high subthreshold swing and degraded transconductance.
RF Degradation
High-frequency performance suffers because the trapped charges cannot respond quickly to rapid signal transitions. This lag leads to gate-lag and drain-lag effects, which show up as a transient drop in output power. When a module experiences this effect, its efficiency during pulsed operation decreases.
Passivation Method
Applying a thin layer of silicon nitride or aluminum oxide via atomic layer deposition helps to satisfy the dangling surface bonds. This passivation step reduces the density of interface traps and restores gate control over the channel. Engineers evaluate the success of this treatment by measuring the capacitance-voltage curves of test structures before proceeding to full wafer dicing.
A stable threshold voltage over long operating cycles indicates that the trapping effects have been neutralized.