Silicon Substrate Surface Conduction and Dielectric Passivation Fundamentals
Trap-rich polysilicon passivation pins interface charges on high-resistivity silicon, suppressing surface conduction and harmonic spur spikes across RF switches.
Parasitical Surface Conduction
Meaning
Unwanted electrical current that flows along the interface between a semiconductor substrate and its insulating dielectric layers degrades the isolation between adjacent nodes on a chip. This parasitical surface conduction primarily affects high-frequency devices where strong electric fields exist near the oxide boundary. Designers must minimize this leakage to maintain transmitter efficiency.
Substrate Action
Interface states and fixed charges within the passivation layer attract mobile carriers to the surface of the silicon. Under radio-frequency voltage swings, this parasitical surface conduction creates a resistive channel that dissipates signal power. This channel bypasses the insulating barrier.
Electrical Impairment
The secondary current path increases insertion loss in passive circuits and degrades the noise figure of transceivers. Because parasitical surface conduction acts as a parallel resistor, it reduces the quality factor of on-chip inductors and transmission lines. This degradation is highly pronounced at millimeter-wave frequencies.
Mitigation Protocol
Introducing a high density of recombination centers near the interface traps these mobile carriers and disables the conduction channel. Engineers employ a layer of trap-rich polysilicon below the oxide to suppress parasitical surface conduction effectively. This processing step ensures that the substrate remains highly resistive during operation, which preserves signal power in high-frequency wireless modules and protects sensitive receive paths.