Meaning
Logic segments within an integrated circuit that lack internal test accessibility through boundary scan chains are grouped for analysis. Designers refer to a non-scan cluster as a collection of gates and registers that must be tested via functional vectors. These blocks often include high speed paths or legacy cores where scan flip flops were not implemented.
They present a challenge for automated test pattern generation.
Test Accessibility
Coverage metrics for these areas are typically lower than for scan enabled logic. In a non-scan cluster, the test patterns must be driven from the inputs of the cluster and observed at the outputs. This requires a sequential understanding of the logic states over multiple clock cycles.
Coverage Calculation
Physical constraints or performance requirements often dictate the exclusion of scan cells from certain areas of a chip. The presence of a non-scan cluster increases the complexity of the overall test plan. Engineers must develop custom functional tests to verify the integrity of these hidden nodes.
This process often involves simulating the exact timing and behavior of the circuit under operating conditions. Failure to test these sections can lead to defects escaping the manufacturing floor and reaching the final product.
Diagnostic Barrier
Isolating a fault within these regions is more difficult than in scan based hardware. When a non-scan cluster fails a functional test, the root cause is often masked by the surrounding logic. It requires sophisticated simulation tools to trace the failure back to a specific gate.
