Meaning
Stability metric representing the maximum amount of noise voltage that can be added to the input of a logic gate without causing an incorrect output state. Static noise margin is a critical parameter for evaluating the reliability of memory cells and logic circuits in high density integrated circuits. Safety margins represent the buffer that protects the signal against cross-coupled interference and power supply fluctuations.
Voltage Transfer
The measurement is typically derived from the voltage transfer curves of the inverters within a storage element like an SRAM cell. Static noise margin corresponds to the side of the largest square that can be nested within the lobes of the butterfly plot. A larger square indicates a more resilient cell that is less likely to flip its state due to external disturbance.
Reliability Assessment
Reduced supply voltages in modern low power designs shrink this buffer, making the system more susceptible to soft errors. The static noise margin must be high enough to withstand the variations in transistor threshold voltages caused by manufacturing tolerances. If the margin drops to zero, the circuit loses its ability to hold data reliably.
Operational Window
Stability of the circuit is tested under both read and write conditions to find the worst case scenario. During a read operation, the static noise margin often decreases because the access transistors disturb the internal nodes of the cell. Proper sizing of the pull up and pull down transistors is the primary method for maintaining an acceptable margin.
