Meaning
Vertically stacked, horizontally planar semiconductor ribbons wrapped entirely by gate dielectric and conductive electrode material define a gate-all-around field-effect transistor architecture. A nanosheet replaces vertical FinFET fins at sub-three-nanometre manufacturing nodes to maintain electrostatic channel control and suppress subthreshold leakage currents. The structure governs drive current scaling, threshold voltage stability and physical cell footprints inside digital baseband processors and high-density connectivity system-on-chip devices.
It describes gate-all-around architectures utilizing wide planar channels, stopping short of horizontal cylindrical nanowires, carbon nanotube networks and two-dimensional transition metal dichalcogenide monolayers.
Channel Geometry
Alternating epitaxial layers of silicon and silicon-germanium grow on a substrate before selective chemical etching removes the sacrificial material to release suspended semiconductor ribbons. Each nanosheet features a rectangular cross-section with width spanning from ten to fifty nanometres and thickness controlled down to atomic precision around five nanometres. Fabricators adjust effective channel width continuously by modifying lithographic masks, bypassing the discrete quantized width restrictions imposed by multi-fin FinFET designs.
Wider sheets supply superior direct-current drive strength for high-speed digital logic, whereas narrower sheets minimize standby leakage inside battery-powered transceivers.
Gate Electrostatics
Enclosing all four sides of the channel with work-function metal stacks guarantees electrostatic gate control over mobile carriers. In a nanosheet field-effect transistor, full gate envelopment prevents drain-induced barrier lowering and minimizes short-channel punch-through effects. Off-state subthreshold swing approaches theoretical physical limits.
Parasitic Capacitance
Dense vertical stacking introduces parasitic capacitance between gate electrodes and adjacent source-drain epitaxial contacts. Because the inner dielectric spacers separating stacked nanosheet channels must be thin, internal fringing fields increase parasitic loading and degrade high-frequency switching figures of merit. Designers balance spacer thickness and nanosheet vertical clearance to optimize the trade off between drive current delivery and circuit delay.
Integration teams account for this parasitic capacitance during timing closure and radio frequency parasitic extraction phases prior to module tape-out.
