Managing Dielectric Tolerances in Dual Sourced Wireless Substrates
Dual sourcing wireless substrates demands matching effective dielectric constants, copper foil profiles, and glass weave structures via IPC-2581 stack-up controls.
Trace Geometry Compensation
Meaning
Pre-distortion CAD modifications alter printed circuit board trace width and spacing on artwork files to offset chemical etching undercut and plating growth during fabrication. Applying trace geometry compensation ensures finished physical conductor dimensions match electrical target impedance values. Chemical etching removes copper laterally under photoresist edges, resulting in a trapezoidal cross-section rather than a rectangular profile.
Adjustment boundaries stop at photolithography resolution limits and minimum clearance spacing rules.
Process Modification
Fabricators expand CAD trace widths on photolithography tooling to anticipate metal removal during wet etching steps. Applying trace geometry compensation corrects for base copper thickness variation and etch factor differences across inner and outer layers. Cross-sectional micro-section analysis measures actual post-etch line widths against design nominals.
Accurate compensation maintains intended differential impedance tolerances across RF lines.
Impedance Control
Trapezoidal trace shapes alter electric field distribution and overall characteristic impedance. Utilizing trace geometry compensation offsets side-etch effects to achieve target fifty-ohm transmission line parameters. Coupon measurements verify that physical impedance matches field solver predictions.
Tooling Offset
Manufacturing engineering rules establish specific offset factors for each copper weight and etching line. Implementation of trace geometry compensation prevents costly artwork revisions after initial panel prototyping. Final tooling files retain detailed etch factor modifications for auditing.