Meaning
Sudden voltage drops occurring during high current demand events can lead to system resets or data corruption if the power delivery network fails to maintain the required logic levels. This phenomenon happens when a large section of the chip, such as a radio power amplifier or a high speed processor core, is turned on simultaneously. The sudden jump in current causes a voltage drop across the resistance and inductance of the power traces and the package pins.
If the voltage falls below the brownout threshold of the device, the internal logic will stop functioning correctly. Transient power collapse is a major design challenge in compact mobile devices where space for decoupling capacitors is limited.
Voltage Sag
Magnitude of the drop is determined by the peak current and the impedance of the power delivery network at that specific frequency. When the current increases rapidly, the inductance of the traces resists the change and causes a momentary dip in the supply voltage. This sag can be very brief, lasting only a few nanoseconds, but it is long enough to flip a bit in a register or cause a timing violation.
If the voltage drops too far, the device may enter a locked state where it no longer responds to any inputs. Transient power collapse is often the root cause of mysterious system crashes that are hard to reproduce in the lab. Engineers use high speed oscilloscopes and specialized power integrity probes to capture and analyze these events.
Reset Trigger
Monitoring circuits inside the chip are designed to detect when the supply voltage falls below a safe level and trigger a hard reset. This prevents the processor from executing corrupted instructions that could damage the hardware or erase the flash memory. While this is a necessary safety feature, frequent resets caused by transient power collapse make the product unusable.
The reset threshold must be carefully chosen to balance the need for safety with the need for system availability. In some cases, the power management unit can provide a warning interrupt to the processor before the reset occurs. This allows the software to save its state and shut down gracefully.
However, if the collapse is too fast, the processor will not have time to react.
Recovery Mechanism
Restoration of the stable power rail must happen quickly to allow the system to reboot and resume operation. The decoupling network must be designed to dampen any oscillations that occur as the voltage recovers from the sag. If the power supply is too slow to respond, the system may get stuck in a loop of constant resets.
Designers use a combination of local ceramic capacitors and larger bulk capacitors to provide a stable response across all frequencies. They also implement software techniques like staggered power up of the internal blocks to reduce the peak current demand. By spreading out the current load over time, they can prevent the transient power collapse from happening in the first place.
The final validation of the power delivery network involves testing the system under worst case software loads.
