Trap Rich Polysilicon Layer Optimization for Harmonic Suppression in Front End Modules
Trap rich polysilicon layers freeze interface charges to hold high resistivity and suppress switch harmonics below minus eighty dBc.
Wafer Bow
Meaning
Macroscopic out-of-plane curvature of a semiconductor substrate occurs due to mechanical stress induced by deposited thin films or thermal gradients. The monitoring of wafer bow is essential to prevent focal-plane errors during subsequent high-resolution photolithography steps. This geometric deformation is bounded by the mechanical yield strength of the silicon and the maximum allowable deflection of the vacuum chucks in the processing equipment, which must be able to securely hold the wafer flat during processing.
Stress Source
Different thermal expansion coefficients between the silicon substrate and the deposited oxide or metal films generate significant stress during cooling. Compressive stress in the film causes a convex curvature, while tensile stress leads to a concave shape. Controlling the deposition conditions is necessary to balance these opposing forces.
Lithography Challenge
Modern stepper systems require extremely flat surfaces to achieve uniform exposure across the entire wafer. High values of this curvature prevent the vacuum chuck from completely flattening the substrate. This results in localized defocusing and patterns that do not meet critical dimension specifications.
Mitigation Method
Process engineers often deposit a compensation layer on the backside of the wafer to counteract the stress of the frontside circuits. Rapid thermal processing must also be optimized to ensure uniform temperature distribution and prevent thermal stress. These steps ensure the wafer remains flat enough for advanced packaging processes.