Meaning
Hardware phenomenon involves the production of transient and erroneous logic states during memory mapping transitions. Address decoder glitching happens when different signals within the decoding logic arrive at different times due to varying path lengths. These pulses are brief but can trigger unintended write or read operations in sensitive memory blocks.
The error ends once the logic gates settle into their final stable state.
Circuit Mechanism
Variations in gate delay and wire capacitance create the conditions for these unwanted pulses. When an address bus changes from one value to another, the internal gates of the decoder might temporarily resolve to a third and incorrect address. This usually happens in high speed designs where the clock cycle is close to the propagation limits of the silicon.
Data Integrity
Corruption of stored information is the primary risk when these transients occur. If a glitch occurs on a write enable line, the system might overwrite a critical register with random data. This can lead to system crashes or unpredictable behavior in smart devices that rely on precise memory states.
Timing Constraint
Addition of synchronization flip flops or the use of Gray code addressing reduces the probability of these errors. Layout designers often ensure that all address lines have matched lengths to minimize skew between bits. Properly constrained timing paths prevent the logic from transitioning through invalid states.
