Meaning
Electrical degradation where the drain current of a field-effect transistor falls below its expected value under high-frequency operation. In power switching circuits, current collapse decreases the efficiency of the device by increasing conduction losses during the on-state transition. This drop in current stems from the slow release of electrons that become trapped in the semiconductor material or at the surface during high-voltage stress.
Trapping Mechanism
Localized charge capture happens when the transistor is subjected to high drain-source voltages during the off-state. The strong electric field drives electrons into donor-type and acceptor-type states in the buffer layers and at the boundary with the overlying dielectric. Once the gate voltage shifts to turn the channel back on, these trapped charges do not escape instantaneously, acting instead as a negative potential that suppresses channel conduction.
This delay in charge release causes a temporary reduction in carrier concentration and mobility.
Testing Method
Dynamic parameter extraction employs a double-pulse system to measure the on-resistance of the device immediately after a period of high-voltage stress. By varying the duration and magnitude of the stress pulse, the tester identifies the specific energy levels of the active traps. A comparison between the static characteristics and the dynamic current-voltage profiles yields the recovery signature of the transistor.
Surface Passivation
Mitigation of the instability requires the chemical termination of surface dangling bonds and the deployment of field plates. Depositing high-quality dielectric layers across the gate region terminates active trap states and shields the surface from high electric fields. Atomic layer deposition of aluminum oxide provides a uniform film that establishes a clean chemical interface, preventing the carrier capturing that initiates current collapse.
