Meaning
Semiconductor transistor architectures that wrap the gate material around all sides of a conducting channel offer superior electrostatic control over sub-micron devices. Adopting the gaafet design enables continued scaling of integrated circuits past the limits of finfet technologies. This configuration minimizes leakage current and enhances drive current in advanced node logic chips.
Structural Configuration
The channel consists of stacked horizontal nanosheets or nanowires made of silicon or silicon-germanium. Surrounding each of these individual channels with the gate dielectric and metal electrode ensures uniform electric field distribution. This complete enclosure maximizes the gate control over the channel region, suppressing short-channel effects that degrade performance in small geometries.
Manufacturing Process
Fabricating these structures involves depositing alternating sacrificial layers of silicon-germanium and active silicon. The sacrificial layers are subsequently etched away using highly selective chemical processes to leave suspended silicon nanosheets. Depositing the high-k dielectric and metal gate materials around these suspended sheets requires atomic layer deposition to ensure uniform coverage in the narrow cavities.
This delicate step determines the threshold voltage uniformity across the wafer.
Electrical Performance
Devices using this technology exhibit lower subthreshold swing and reduced drain-induced barrier lowering compared to older geometries. The improved control allows the operating voltage to be reduced, which significantly lowers the dynamic power consumption of mobile and server processors. Scaling these transistors allows the integration of more processing cores within a fixed thermal envelope.
This efficiency enables the performance gains required by modern computing platforms.