Trap Rich Polysilicon Layer Optimization for Harmonic Suppression in Front End Modules
Trap rich polysilicon layers freeze interface charges to hold high resistivity and suppress switch harmonics below minus eighty dBc.
Grain Boundary Defect Density
Meaning
Concentration of localized electronic defect states located at the interfaces between crystallites in a polycrystalline material determines the charge transport behavior. A high grain boundary defect density creates electrical barriers that impede carrier mobility and increase the recombination of charge carriers. This metric is bounded by the average grain size of the material and the effectiveness of chemical passivation steps, which represents the limit where grain boundaries no longer dominate the electrical resistivity.
Charge Impedance
Disordered atomic arrangements at the grain boundaries create trapping centers for free carriers. These trapped charges set up electrostatic potential barriers that carriers must overcome to conduct current. The resulting resistance degrades the performance of thin-film transistors and polycrystalline silicon gates.
Passivation Method
Fabrication processes use hydrogen plasma annealing to pacify these localized defect states. Hydrogen atoms diffuse into the grain boundaries and bond with silicon dangling bonds, which neutralizes their electrical activity. This treatment lowers the potential barrier and increases the carrier mobility.
Substrate Influence
Deposited layers with larger grains have fewer boundaries per unit area and therefore exhibit lower overall defect densities. Controlling the deposition temperature and post-deposition annealing allows engineers to optimize the grain structure. This reduction in defect density is critical for reducing leakage currents in high-density memory arrays.