Meaning
Memory-mapped pointer tables contain the explicit memory start addresses of executable subroutines dedicated to handling asynchronous hardware and software events. In microcontroller architectures, an interrupt vector provides the bridge between an external hardware trigger and its associated interrupt service routine. When a peripheral asserts an interrupt line, the processor hardware looks up the corresponding address in this table and branches immediately to that instruction address.
This mechanism provides deterministic response times to critical events such as timer overflows, communication interface byte receptions, and fault conditions. The vector itself represents only the target entry address and ceases to govern execution once the central processor begins executing the service routine instructions.
Hardware Redirection
Exception handling begins when an internal peripheral or external pin asserts a hardware interrupt signal to the processor core. The hardware interrupt controller evaluates the request against current priority levels, saves critical execution registers onto the system stack, and reads the memory address stored at the assigned table offset. The program counter is then loaded with this vector address, transferring execution directly to the service handler without software-driven branching loops.
Upon completion, the handler executes a return instruction, restoring the saved register context and resuming interrupted program execution.
Table Configuration
System firmware configures vector tables in non-volatile memory or relocates them to volatile SRAM during startup using vector table offset registers. Placing the table in volatile memory enables dynamic updates to vector targets at runtime, supporting dynamic driver initialization and operating system task scheduling. Developers write vector tables inside startup assembly or low-level C files, ordering the function pointers to match the physical hardware interrupt layout defined by the microcontroller manufacturer.
If an unhandled interrupt fires and points to a null vector, the processor enters an unrecoverable hard fault state.
Timing Verification
Response determinism is validated by measuring interrupt latency with digital oscilloscopes and hardware logic analyzers. Test programs drive external trigger pins while tracking the precise time delay until the first instruction of the service routine toggles a designated general-purpose output pin. Automated test suites verify that all table entries point to valid executable code boundaries and contain no unmapped memory references.
Validating vector execution behavior ensures that critical real-time events meet strict latency constraints under maximum system processing loads.
