Correlation Mechanics for Transferred Analog Block Yield Distributions across Secondary Wafer Foundries
Transferring analog blocks across secondary foundries requires mapping PCM covariance matrices to maintain targeted circuit yield distributions.
Shallow Trench Isolation Stress
Meaning
Mechanical pressure exerted by insulating oxide structures on the adjacent silicon regions of a transistor affects the mobility of charge carriers. This shallow trench isolation stress is a consequence of the different thermal expansion coefficients of silicon and silicon dioxide. It alters the atomic lattice spacing, which can either increase or decrease the speed of the device depending on the direction of the force.
The effect is most pronounced in small geometry nodes where the isolation trenches are very close to the channel.
Lattice Strain
Compression or tension in the silicon crystal changes the energy bands of the semiconductor. When shallow trench isolation stress is managed correctly, it can be used to enhance the drive current of transistors. Unmanaged stress leads to unpredictable timing.
Mobility Shift
Carrier velocity is linked to the amount of strain in the lattice. Because shallow trench isolation stress varies with the distance from the trench edge, identical transistors can have different performance characteristics based on their layout. Layout dependent effects must be modeled during circuit design.
Threshold Variation
The voltage required to turn on the transistor shifts in response to the mechanical load. High levels of shallow trench isolation stress can cause the threshold voltage to deviate from the target value. This deviation increases the leakage current of the chip.