Internal Low Frequency Relaxation Oscillator Drift Mechanics in Sleep Modes

Physics

Integrated relaxation oscillators establish a low-frequency reference by repeatedly charging and discharging an internal capacitor through a resistor network. In ultra-low-power wireless MCUs and SoCs, this internal low-frequency oscillator provides the sleep clock while high-frequency crystal oscillators stay off to save power. The target frequency is 32.768 kHz, matching traditional watch crystals.

Generating that clock on-chip without an external crystal introduces substantial drift driven by semiconductor physics, supply voltage noise, and ambient thermal shifts.

An RC relaxation oscillator uses a current source to charge an integrated capacitor up to a threshold defined by an internal bandgap reference. When the capacitor hits that threshold, a comparator triggers a discharge switch to reset the cycle. Output frequency depends directly on capacitance, resistance, reference voltage, and comparator propagation delay, while thermal noise adds timing jitter.

Temperature shifts cause non-linear frequency variation because poly-silicon resistors and integrated capacitors both have non-zero temperature coefficients. Poly-silicon resistors carry tempcos anywhere from hundreds to thousands of ppm/°C, depending on doping levels and process node. Integrated capacitors ~ whether metal-insulator-metal or MOS structures ~ introduce their own temperature dependencies along with parasitic capacitance shifts from substrate depletion layers.

Left uncompensated, an internal relaxation oscillator can drift more than ±20,000 ppm across an industrial temperature range of -40°C to +85°C.

Supply voltage variations add another layer of drift. When a chip enters deep sleep, the power management unit throttles voltage regulators, dropping supply rails from active levels (typically 1.8V to 3.3V) down to 1.0V ~ 1.2V or switching an LDO into pulse-frequency modulation mode. Voltage ripple on the sleep rail directly modulates the charging current fed to the capacitor.

At the same time, shifts in supply voltage alter the comparator’s threshold voltage. In unregulated relaxation topologies, a 100 mV rail variation causes frequency shifts of 0.5% to 2.0%.

Process variation and silicon aging introduce fixed initial offsets and long-term random drift. Die-to-die variations during fabrication leave uncalibrated low-frequency oscillators with initial frequency errors of ±10% to ±20%. Packaging then adds mechanical stress to the die, shifting resistor values through piezoresistive effects.

Over years in the field, bias temperature instability and hot carrier injection shift transistor threshold voltages inside the comparator, causing permanent frequency drift.

Dynamic thermal gradients drive short-term drift during sleep-wake cycles. While active, the radio’s power amplifier and digital cores heat the silicon die rapidly. Once the MCU enters deep sleep, power dissipation drops by three to four orders of magnitude, and junction temperature cools toward ambient.

Because the oscillator sits inside a continuous thermal transient for the duration of the sleep cycle, its frequency drifts continuously rather than settling at a fixed rate.

Uncompensated internal relaxation oscillators exhibit thermal drift exceeding 20000 ppm across industrial temperature limits without active factory or runtime calibration.

Flicker noise and thermal noise in the charging transistors cause pulse-to-pulse jitter and phase noise. High-frequency phase noise averages out across the thousands of cycles in a sleep interval, but low-frequency 1/f noise shifts baseline timing over multi-second windows. This 1/f noise sets a hard floor on the timing precision an internal relaxation clock can achieve, regardless of supply rail cleanliness or compensation schemes.

To counter these drift sources, microcontrollers incorporate several hardware mechanisms:

• Temperature-compensated current mirrors generate charging currents with positive or negative thermal coefficients designed to cancel out the primary temperature coefficient of the RC network.
• Digitally controlled capacitor arrays adjust effective timing capacitance during runtime calibration routines driven by hardware timers.
• Regulated internal power domains isolate the oscillator from main supply fluctuations and LDO switching ripple during deep sleep.
• Hardware-assisted calibration logic counts high-speed crystal cycles during active wakeups to calculate correction factors for the sleep timer.

When relaxation oscillators drift out of spec, failures show up across both hardware and network protocols:

• Thermal gradient tracking failure occurs when rapid temperature shifts outpace calibration intervals, degrading sleep timer accuracy between active windows.
• Voltage regulator ripple intermodulation occurs when LDO switching frequencies beat against the oscillator fundamental, creating sideband noise and timing jitter.
• Comparator offset hysteresis drift happens when prolonged sleep at high temperatures shifts comparator bias thresholds, systematically changing the period.
• Process corner saturation limits capacitor array adjustment range on chips at extreme process corners, preventing full correction at temperature extremes.

Datasheets often highlight factory-calibrated accuracy of ±500 ppm at 25°C, but footnote tables usually clarify that thermal drift across the full operating range reaches ±5,000 ppm unless firmware runs periodic recalibration against an active high-frequency crystal.

Window

Synchronized wireless protocols rely on periodic listening windows to maintain communication between nodes. In star and mesh networks, sleeping end-devices wake up on schedule to listen for beacons, preambles, or polling requests from gateways or base stations. When the sleep timer is driven by a drifting relaxation oscillator, the expected arrival time of a frame becomes uncertain.

The receiver has to open its RF window early and keep it open longer to avoid missing the transmission ~ a buffer referred to as guard time expansion or receiver window widening.

The required guard time depends on the combined timing uncertainty of both the transmitter and receiver clocks. The minimum guard time follows a simple linear expansion:

T_guard = 2 T_sleep (PPM_tx + PPM_rx) + T_jitter + T_latency

Here, T_sleep is the continuous sleep duration between active events, PPM_tx and PPM_rx are the frequency tolerances of the transmitter and receiver clocks in parts per million, T_jitter covers short-term phase noise and jitter, and T_latency accounts for hardware wakeup delays like regulator settling times and PLL lock durations.

In Bluetooth Low Energy (BLE) peripherals, connection events occur at negotiated intervals between 7.5 milliseconds and 4.0 seconds. Between events, the peripheral relies on its sleep clock to hit the next anchor point. The BLE specification caps window widening at 500 microseconds.

If drift pushes required window widening past 500 microseconds, the device must wake up more frequently to re-synchronize or risk dropping the link to a supervision timeout. An internal oscillator with ±250 ppm drift paired with a ±50 ppm central yields a combined uncertainty of 300 ppm. On a 1.0-second connection interval, that requires a 600-microsecond guard window ~ exceeding BLE limits and forcing early wakeups that drain the battery.

LoRaWAN Class A devices open fixed receive windows, RX1 and RX2, at 1.0 and 2.0 seconds after an uplink. Between uplinks or join requests, devices may sleep for hours or days. At SF12 with a 125 kHz bandwidth, a single LoRa symbol takes 32.768 milliseconds, and preamble detection requires the receiver to stay active for at least 5 symbol periods (163.84 ms).

If an internal relaxation oscillator drifts by ±1,000 ppm over a 24-hour sleep window, timing error accumulates to 86.4 seconds. That degree of drift completely misses the downlink window, forcing full re-join procedures and heavy energy costs.

Is Guard Time Expansion Predictable over Long Sleep Intervals?

Thermal transients create non-linear drift during deep sleep. Simple calculations treat clock drift as linear based on a static ppm spec, but real deployments expose nodes to sharp temperature changes. An outdoor solar sensor or asset tracker going from direct sunlight to shade experiences rapid board temperature shifts.

Because the oscillator’s frequency responds non-linearly to temperature, actual drift follows a curve over time, rendering linear guard-time formulas inaccurate and leading to dropped packets or over-extended receive windows.

Cellular IoT standards like LTE-M (eDRX) and NB-IoT (PSM) impose tight timing bounds over long sleep intervals. In eDRX, an LTE-M device can sleep for up to 40.96 minutes at a time, waking periodically within a Paging Time Window (PTW) to catch paging frames from the base station. 3GPP standards leave little margin for timing misalignment.

If the sleep clock drifts outside the PTW, the device misses its page, the base station flags it as unreachable, and recovery requires a full cell search, SIB re-acquisition, and NAS re-attach on the next wakeup.

Standard protocol compliance guidelines enforce a 500 microsecond absolute ceiling on Bluetooth Low Energy sleep window widening before active connection loss occurs.

To keep window widening from destroying battery life, firmware engineers follow a few standard practices when setting up guard timing:

1. Quantify physical layer symbol boundaries by matching minimum preamble detection lengths to demodulator lock times for the chosen modulation scheme.
2. Extract baseline temperature coefficients across the operating range using thermal chamber sweeps at nominal supply voltage.
3. Define worst-case sleep limits so receiver guard time stays under 10% of the total sleep energy budget.
4. Implement dynamic guard window scaling in firmware to adjust listening windows based on board temperature changes.
5. Establish automatic re-sync triggers that force short wakeups to refresh timing whenever temperature shifts cross a set threshold.

Ignoring relaxation oscillator drift when sizing receive windows leads directly to premature battery failure, as the radio spends far too much power listening in oversized guard windows.

Charge

In sleeping sensor nodes, preamble searching is often the single largest draw on battery life. Choosing an internal low-frequency relaxation oscillator over an external 32.768 kHz crystal comes down to a trade-off between baseline sleep current and active calibration energy. The internal oscillator draws very little quiescent current ~ typically 100 nA to 500 nA in deep sleep ~ whereas an external crystal circuit draws 1.0 µA to 2.5 µA continuously to power the inverter and sustain oscillation.

That savings in nanoamperes comes with hidden costs. Because an internal oscillator drifts with time and temperature, the MCU has to wake up periodically to calibrate it. A typical calibration cycle turns on the high-frequency crystal (16 MHz to 32 MHz), enables a hardware counter, and runs for a few milliseconds to count high-speed cycles against a set number of low-frequency ticks.

That ratio yields a digital correction factor applied to the sleep timer.

The energy cost of each calibration is significant. A 32 MHz crystal and its digital counters draw 3.5 mA to 8.0 mA while starting up and running. If a calibration run takes 5.0 milliseconds at 3.3V, a single cycle consumes:

E_cal = 3.3 V 0.005 A 0.005 s = 82.5 microjoules

If temperature shifts force this calibration to run every 2.0 seconds to maintain ±250 ppm accuracy, the average calibration power is:

P_cal_avg = 82.5 uJ / 2.0 s = 41.25 microwatts

At 3.3V, 41.25 microwatts corresponds to an effective continuous current penalty of 12.5 microamperes. That overhead completely erases the 1.5 microampere sleep current savings from dropping the external crystal, raising overall power consumption significantly.

Where the energy crossover sits between a calibrated internal oscillator and an external crystal depends on sleep duration and radio duty cycle. On short sleep intervals under 10 seconds, recalibrating repeatedly costs far more power than running an external crystal continuously. On long sleep intervals of tens of minutes or hours ~ where calibration only runs right before an active event ~ the internal oscillator can deliver genuine net savings.

Calibrating an internal relaxation oscillator in firmware requires a predictable sequence:

1. Set thermal sensor interrupts to detect temperature shifts during sleep.

2. Start the high-frequency crystal oscillator ahead of planned radio events.

3. Wait for crystal stabilization and PLL lock.

4. Feed the high-speed clock and low-frequency sleep clock into hardware counters.

5. Count high-speed ticks across a fixed number of sleep clock periods to measure the frequency ratio.

6. Calculate the fractional error and update sleep timer compensation registers.

7. Shut down the high-frequency crystal and return to sleep.

Frequent calibration wakeups consume far more battery energy than the continuous power draw of an external crystal oscillator.

Sleep clock drift can be evaluated by monitoring active window expansion on current probes. In cold chamber testing, disabling dynamic calibration reduced battery life by 45 percent. That drop was caused directly by the receiver turning on early to catch packet preambles when the clock drifted at low temperatures.

Master supply agreements and purchase orders often include specific clock stability terms:

Clause 8.4: The silicon vendor guarantees internal relaxation oscillator frequency drift shall not exceed ±500 ppm across the temperature range of -20°C to +70°C under continuous auto-calibration mode, provided calibration execution intervals do not exceed 5.0 seconds and supply voltage regulation remains within ±5% of nominal 3.3V levels.

If battery calculations ignore the energy spent on calibration wakeups, field lifespan estimates fall apart, leading to early failures long before devices reach their target service life.

Bench

Measuring low-frequency oscillator stability in deep sleep requires equipment that combines sub-microamp current resolution with fast frequency logging. Standard multimeters and bench oscilloscopes cannot accurately capture sleep drift ~ their input loading and sampling rates blur microamp pulses and obscure millisecond timing edges. Characterizing these oscillators requires a test setup that isolates thermal, electrical, and mechanical effects.

The bench setup centers on a source measure unit (SMU) or power profiler capable of sampling at 100 ksps or higher with sub-nanoamp resolution. The SMU powers the MCU while recording current waveforms. To track real-time jitter and cumulative drift, an internal GPIO is toggled on sleep entry and exit, or configured to output a divided clock signal (such as 1 Hz or 1024 Hz) to an external counter or oscilloscope.

For thermal sweeps, the DUT goes into a temperature chamber programmed for controlled ramps between -40°C and +125°C (often at 1°C/min). Power cables, probe leads, and clock monitor lines entering the chamber need low-capacitance, shielded wiring to avoid parasitic loading on high-impedance oscillator nodes. The board sits on thermal isolation mounts so metal surfaces in the chamber do not sink heat away from the package and distort junction temperatures.

Allan deviation is the standard metric for evaluating short-term stability and phase noise in low-frequency sleep clocks. Unlike standard deviation, which assumes stationary Gaussian noise, Allan deviation measures fractional frequency variation across different observation times. Plotted against cluster time, it reveals distinct noise sources: white phase noise dominates below a millisecond, flicker phase noise flattens the curve around milliseconds, white frequency noise shows up on second scales, and thermal random-walk drift turns the curve back upward over multi-second windows.

Thermal chamber testing builds empirical guard models and specifies drift tolerances in vendor contracts to avoid packet drops in the field. Standard test suites cover both steady-state temperatures and thermal transients during rapid power state changes.

Qualification dossiers for new modules typically include standard test data verifying clock performance under load:

• Full-temperature Allan deviation plots covering integration times from 1 millisecond to 1,000 seconds.
• Power supply rejection profiles mapping oscillator frequency shifts against supply ripple from 10 Hz to 1 MHz.
• Dynamic thermal response logs tracking clock drift through high-power radio bursts and subsequent sleep cooling.
• Long-term aging projections based on 1,000-hour HTOL testing at +125°C.

Testing relaxation oscillator stability requires measuring frequency drift while simultaneously profiling microampere sleep current waveforms across thermal ramps.

Room-temperature drift measurements tell you almost nothing about how a relaxation oscillator will perform at temperature extremes in the field.

Sourcing

Datasheet sleep figures are almost always quoted at room temperature with ideal clock settings. When sourcing wireless SoCs for volume production, teams need to look beyond headline specs and weigh the real cost of clock accuracy choices. Relying solely on an internal relaxation oscillator saves $0.06 to $0.12 per unit by leaving off a 32.768 kHz crystal and two load capacitors.

That small BOM saving can easily create major liabilities down the line. If uncompensated thermal drift reaches ±2,500 ppm in the field, receiver guard windows must expand, boosting average power draw by three to five times. For a battery-powered meter or asset tracker, that cuts field life from ten years to under three.

Truck rolls to replace depleted lithium batteries cost $50 to $150 per site ~ wiping out the initial twelve-cent savings instantly.

Carrier certification and regulatory standards also impose strict clock limits. Acceptance testing for LTE-M and NB-IoT devices requires compliance with 3GPP TS 36.133 frequency stability specs. Modules using uncalibrated sleep clocks often fail paging sensitivity tests, blocking network approval and preventing deployment in key markets across North America, Europe, and Asia-Pacific.

Sourcing teams should include explicit clock specs in RFQs and master service agreements, requiring vendors to commit to hard performance bounds under real-world conditions rather than “typical” ratings:

• Guaranteed maximum drift across -40°C to +85°C with active calibration, specified as a hard cap rather than a typical value.
• Calibration energy caps defining maximum active time and current draw for calibration routines.
• Supply voltage coefficients bounded across the full battery discharge curve (e.g., 3.6V down to a 2.1V cut-off).
• Aging guarantees capping drift after 10 years at elevated operating temperatures.

Choosing between internal oscillators and external crystal references ultimately comes down to balancing production volume against environmental conditions and battery lifetime goals.

For low-power system architects, the fundamental question is simple: at what thermal slew rate and sleep interval does the energy cost of software calibration exceed the hardware cost and baseline current of an external crystal?