Meaning
An industry standard that extends boundary scan capabilities to high-speed, AC-coupled differential signaling lines governs modern digital interface testing. This ieee 1149.6 specification defines the test receiver architectures and test patterns necessary to verify high-bandwidth links that utilize serial capacitors. It allows testing of advanced communication buses without requiring direct DC paths between transmitter and receiver.
Boundary Architecture
The standard introduces specialized boundary scan cells equipped with dynamic transmitters and receivers. These cells generate and detect transient pulses rather than static voltage levels. This behavior allows the test signals to pass through the coupling capacitors that block standard DC signals.
Signal Transmission
Pulse-based signaling methods ensure that the transition events are captured before the signal decays. The transmitter sends a structured pulse train that the receiver analyzes for transitions. This approach detects open pins, shorts to ground and crossed differential pairs.
Diagnostic Benefit
Implementing this standard eliminates the blind spots that exist in traditional boundary scan routines on high-speed interfaces. It provides precise fault localization on boards that feature serial gigabit links, such as PCI Express or Ethernet interfaces. By identifying the exact failing lane, the standard saves substantial debugging time during system integration.
This diagnostic precision is essential for maintaining high yield in complex networking equipment.
