Meaning
Physical tension applied to the silicon wafer during fabrication to improve the mobility of charge carriers. Controlled silicon substrate strain is a deliberate engineering technique used to enhance the performance of CMOS transistors without reducing their size.
Mobility Enhancement
By altering the atomic spacing, silicon substrate strain reduces the intervalley scattering of electrons and the interband scattering of holes within the semiconductor material. This change in the energy band structure results in a measurable boost to the transconductance of both p-type and n-type devices. Higher carrier mobility translates into lower power consumption for the same performance level, making it an effective technique for extending battery life in mobile connectivity hardware.
Manufacturing Method
Depositing a layer of silicon germanium over the base wafer induces silicon substrate strain by forcing the silicon atoms to align with a slightly larger lattice. Another common approach involves using specialized capping layers that pull or push on the gate structure after the transistor is formed.
Reliability Risk
Excessive silicon substrate strain can lead to the formation of dislocations or defects that increase the leakage current of the device. The use of silicon substrate strain requires a balance between performance gains and the potential for reduced yield or shortened operational lifespan.