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Fractional-N Synthesizer
Meaning
Frequency generation circuit produces an output signal that is a non-integer multiple of a stable reference clock by rapidly switching the feedback divider between two or more integer values. This capability allows a radio transmitter to tune to a much finer resolution of frequencies than a standard integer-n synthesizer could achieve. By using a fractional-n synthesizer, engineers can select the exact center frequency required for various global radio standards without changing the reference crystal.
This flexibility is achieved through the use of a delta-sigma modulator that controls the timing of the divider switching. While this introduces some quantization noise, modern designs use advanced filtering to maintain high signal purity. This component is found in almost every modern wireless module, from Bluetooth to high speed cellular modems.
Frequency Resolution
Precision of the tuning is the primary advantage of this architecture over traditional designs. Because the effective division ratio can be any value between two integers, the fractional-n synthesizer can generate frequencies with sub-hertz accuracy. This resolution is necessary for narrow band communication systems that must squeeze many channels into a small portion of the spectrum.
It also allows the system to compensate for the slight frequency offsets that occur as the reference crystal ages or changes temperature. By making small adjustments to the fractional value, the radio can stay perfectly locked to the intended channel. This fine control ensures that the receiver can maintain a stable lock on the incoming signal even in challenging conditions.
Phase Noise
Quality of the output signal is often limited by the jitter and noise introduced by the switching process. A fractional-n synthesizer can suffer from spurious emissions, or spurs, which appear as unwanted signals at specific offsets from the carrier. These spurs are a direct result of the periodic nature of the fractional division.
Designers must use a high order delta-sigma modulator to randomize the switching and push this noise to higher frequencies where it can be easily filtered. If the phase noise is too high, it will degrade the error vector magnitude of the transmitter and reduce the sensitivity of the receiver. Balancing the loop bandwidth of the circuit is a trade off between the lock time and the noise performance.
Divider Logic
Internal mechanism that handles the switching requires high speed digital circuitry that can operate at the full frequency of the voltage controlled oscillator. The fractional-n synthesizer uses a dual modulus prescaler that can divide by N or N plus one based on the control signal from the modulator. This logic must be extremely fast and consume as little power as possible to be suitable for mobile devices.
The average division ratio over many cycles determines the final output frequency. If the logic fails to switch at the correct moment, the frequency will drift and the communication link will fail. Testing these circuits involves measuring the spectral purity and the time it takes for the synthesizer to hop between different channels.
This performance is a critical part of the radio frequency qualification process for any new connectivity hardware.