Trap Rich Polysilicon Layer Optimization for Harmonic Suppression in Front End Modules
Trap rich polysilicon layers freeze interface charges to hold high resistivity and suppress switch harmonics below minus eighty dBc.
Thermal Budget
Meaning
Cumulative thermal energy administered to a semiconductor wafer during the entire sequence of fabrication steps represents the limit of high-temperature processing. The management of thermal budget prevents the unwanted diffusion of dopants and the degradation of pre-existing materials. This budget is bounded on the lower end by the energy needed to activate dopants or deposit high-quality films and on the upper end by the melting point of the integrated metals, which prevents any further high-temperature processing once metallization is complete.
Dopant Control
Dopant profiles are easily altered by high-temperature steps, which changes channel lengths of transistors. Minimizing the duration and temperature of annealing steps is necessary to maintain sharp junction profiles. Rapid thermal annealing is frequently used to activate dopants while minimizing the overall heat load.
Interface Protection
Integrated substrates with co-deposited metal or trap-rich polysilicon layers can be degraded by excessive heat. High temperatures can cause recrystallization of damaged layers, which reduces their effectiveness. This restricts the maximum temperature allowed during subsequent dielectric deposition.
Backend Integration
Metallization layers using copper or aluminum cannot tolerate the high temperatures used in frontend processing. Once these metal lines are deposited, all subsequent processing must be kept below four hundred degrees Celsius. This constraint forces the use of low-temperature plasma-enhanced deposition methods.