Meaning
The evaluation of high-frequency circuit performance before the individual silicon dies are cut from the wafer prevents the packaging of defective parts. Performing wafer level RF screening identifies faulty integrated circuits early in the manufacturing flow, saving substantial packaging and assembly costs. This process utilizes specialized probe cards to establish electrical contact with the microscopic pads of each die.
Screening Efficiency
Discarding defective silicon at the wafer stage avoids the expenses associated with encapsulating and testing broken chips. This early filtering is particularly valuable for multi-chip modules, where a single bad die would ruin the entire finished assembly. A reliable wafer level RF screening routine thus stabilizes the final production yield of the module.
Equipment Challenge
High-frequency testing on a wafer requires extremely precise probe placement and calibration to compensate for the effects of the cables and probes. Probe tips must make consistent contact with the wafer pads without causing physical damage to the delicate metal structures. Any variation in contact resistance can lead to false failures and lower the calculated wafer yield.
Test Sequence
The automated system performs a rapid series of measurements including scattering parameters, noise figure, and output power on each die. These results are mapped to a wafer database, creating a digital file that guides the dicing machine to select only the passing dies for packaging. Incorporating these tests into the foundry workflow provides immediate feedback on process variations and helps engineers to tune the fabrication parameters.
This proactive feedback loop minimizes wafer-to-water performance variations, maintaining a high standard of product consistency throughout large production runs.