Trap Rich Layer Physics for RF Silicon Substrates
Trap-rich polysilicon layers beneath buried oxide pin interface carriers to eliminate parasitic conduction and lower sub-6 GHz harmonic generation.
Trap-Rich Silicon Substrates
Meaning
Substrate technology incorporating an engineered layer to neutralize parasitic conduction. Wafers classified as trap-rich silicon substrates incorporate a high density of crystal defects near the surface to pin the mobile charge carriers. This modification prevents the formation of a conducting inversion layer that would otherwise increase signal loss at high frequencies.
They are primarily used in the production of radio frequency switches and power amplifiers for cellular communications.
Defect Engineering
Introducing a layer of polysilicon or an ion-implanted region creates the necessary trapping sites. In trap-rich silicon substrates, these sites capture the free electrons that are attracted to the interface by the fixed charges in the oxide layer. This action maintains the high resistivity of the bulk material even under high-power operating conditions.
The stability of these traps is essential for ensuring that the substrate performance does not degrade over the life of the device.
Signal Linearity
Harmonic distortion is reduced when the substrate cannot form a non-linear capacitor. Using trap-rich silicon substrates allows for the integration of high-performance passive components alongside active circuitry.
Handover Metric
Verification of the wafer quality involves measuring the effective resistivity and the second harmonic distortion of a test structure. Devices built using trap-rich silicon substrates must demonstrate a measurable reduction in signal coupling between adjacent circuit elements to pass the inspection. This performance benefit is quantified during the design phase of the front-end module to justify the higher cost of the specialized wafer.
Final production wafers are checked for uniformity to ensure consistent signal integrity across the entire batch.