Meaning
An industry standard for testing printed circuit boards and debugging integrated circuits defines a dedicated hardware interface and protocol for boundary scan testing. In practice, JTAG allows developers to inspect the state of internal registers and flash memory on microcontrollers and field programmable gate arrays. This is achieved by shifting test vectors through a serialized chain of boundary scan cells that sit between the core logic and the physical pins of the device.
This capability enables rapid diagnostic routines on assembled boards without requiring physical oscilloscope probes.
Physical Interface
The connection is established using a set of dedicated pins that include Test Clock, Test Mode Select, Test Data In, and Test Data Out. A fifth optional pin provides an asynchronous reset to the test access port controller. During PCB layout, designers route these signals to a dedicated header or test points that are accessible by boundary scan equipment.
The JTAG controller on the silicon die interprets the serial commands and manages the shifting of data through the boundary registers. This localized control allows test sequences to run at high speeds regardless of the board’s complexity.
Boundary Scan
Scan test routines verify electrical continuity between devices on the board. The testing software drives pins on one chip and samples them on another. This detects short circuits and open traces.
These automatic routines significantly reduce factory test times.
Debugging Capability
Firmware developers run debugging sessions. They set hardware breakpoints and trace instruction execution.
