Trap Rich Polysilicon Layer Optimization for Harmonic Suppression in Front End Modules
Trap rich polysilicon layers freeze interface charges to hold high resistivity and suppress switch harmonics below minus eighty dBc.
Argon Ion Implantation
Meaning
Subsurface modification via noble gas bombardment creates high-density lattice damage to suppress parasitic conduction in silicon-on-insulator wafers. Utilizing argon ion implantation introduces neutral defects that act as recombination centers without altering the chemical doping of the semiconductor. The process is bounded by the threshold where complete amorphization of the active silicon layer occurs, and it must avoid degrading the overlying thin silicon layer where active transistors are fabricated.
Defect Engineering
Ion collisions with the silicon lattice displace atoms from their stable crystal sites to produce interstitial-vacancy pairs. These stable defects remain active after subsequent low-temperature thermal steps. The resulting localized disruption prevents the formation of a mobile charge layer at the oxide boundary.
Material Integration
Substrate preparation for radio-frequency circuits incorporates this step before the deposition of the top active layer. Precision beam alignment prevents unwanted channeling through the crystal planes. This creates a uniform trap-rich zone directly beneath the buried oxide layer.
Thermal Stability
Thermal treatment must be carefully controlled to prevent the unwanted recrystallization of the damaged region. Excessive temperatures during backend metallization can anneal out the implanted defects, which restores the unwanted electrical conductivity. The process window is therefore constrained by the subsequent thermal budget of the chip.