Unbundled Engineering Deliverables in Semicustom Module Sourcing

Split

Semicustom module sourcing sits between standard off-the-shelf building blocks and fully custom hardware development. Hardware teams choose semicustom designs when standard radio modules, system-on-modules, or integrated power stages provide eighty percent of what they need, but fall short on physical footprint, thermal dissipation, antenna geometry, or specialized interfaces. The main commercial friction in this procurement model comes down to non-recurring engineering fees and asset delivery schedules.

Vendors often offer low initial engineering fees or roll customization costs directly into per-unit module pricing. This bundled approach hides the true cost of customization inside inflated hardware margins while withholding essential design files, firmware repositories, and manufacturing test scripts.

Unbundling engineering deliverables splits physical component supply from the intellectual property generated during customization. When a buyer pays for semicustom engineering, the work yields distinct physical and digital assets. Contracting for unbundled deliverables secures clear transfer rights to native CAD files, uncompiled firmware source trees, bill-of-materials databases, thermal models, and automated test routines.

Without explicit unbundling, the buyer receives a finished part but stays locked into a single supplier, needing vendor approval for any design change, second-sourcing attempt, or failure analysis.

Mandating unbundled deliverables changes how engineering hours are quoted, verified, and invoiced. Vendors quoting an unbundled engagement have to itemize engineering hours across schematic edits, PCB layout revisions, board support package updates, thermal modeling, and test fixture design. That transparency removes hidden margin padded into non-recurring engineering quotes.

It forces the supplier to spell out exact file formats, toolchain versions, and acceptance criteria upfront when signing the contract, rather than during handover.

Unbundling changes the procurement risk profile across four main engineering domains.

• Native CAD schematics including complete symbol libraries, nets, differential pair rules, and constraint manager files matching the target EDA environment rather than flat PDF exports.
• Manufacturing artwork and drill files formatted to IPC-2581 or ODB++ standards with explicit layer stack-up definitions, dielectric constants, copper weight targets, and controlled impedance tracks.
• Firmware source code repositories containing uncompiled register-level drivers, board support packages, peripheral initialization routines, linker scripts, build configuration scripts, and target toolchain versions.
• Automated test fixture designs comprising bed-of-nails mechanical CAD models, pin assignment tables, interface card schematics, test executive scripts, and calibration reference data.

Unbundled sourcing shifts technical ownership back to the buyer. If lead times stretch or a vendor faces production outages, an unbundled deliverable package lets another contract manufacturer build the module without redesigning it from scratch. Hardware programs that accept opaque engineering packages trade away supply chain control just to save on upfront development capital.

Unbundled deliverables turn vendor claims into verified engineering assets capable of surviving supplier insolvency or factory migration.

A buyer who fails to mandate unbundled deliverables stays exposed to price increases during production. Suppliers holding sole custody of layout files and firmware source code often reject customer-proposed component swaps, forcing host-board redesigns whenever a passive component or low-dropout regulator reaches end-of-life. The cost of emergency redesigns, re-qualification, and missed market windows quickly wipes out any initial savings on NRE.

Stack

A semicustom module’s physical structure determines its RF performance, thermal limits, and manufacturing yield. Semicustom projects frequently run into trouble during hardware transfer because buyers accept manufacturing output files instead of native design databases. Flat Gerber RS-274X files let a PCB fab house image copper, drill holes, and apply solder mask, but they prevent an engineering team from rerouting traces, adjusting decoupling capacitors, changing pad sizes, or running netlist-level signal integrity simulations.

Native CAD files from Altium Designer, Cadence Allegro, or Siemens Xpedition contain the design intent, rules, copper pour parameters, and library links needed to maintain and modify the hardware.

Layer stack-ups mark a major technical boundary in RF and high-speed digital modules. Vendors building semicustom RF front-end modules usually pick substrate materials and layer counts that suit their own production lines rather than the host system. A six-layer stack-up using standard FR-4 behaves very differently in microstrip impedance, dielectric loss, and heat dissipation compared to a four-layer board built on high-frequency hydrocarbon laminates like Rogers RO4350B.

Native design databases expose pre-preg thicknesses, copper foil roughness, core dielectric constants (Er), and loss tangents (Tan d) necessary to verify signal integrity at the board level.

Component choices inside semicustom modules carry hidden risks when bill-of-materials management stays bundled. Suppliers working under fixed-price NRE contracts often pick passives, inductors, and crystal oscillators based on immediate stock or low cost rather than temperature ratings or long-term availability guarantees. An unbundled engineering scope requires a complete, unblinded bill of materials detailing exact Manufacturer Part Numbers (MPNs), approved vendor lists (AVL), secondary part numbers, tolerances, temperature coefficients, and moisture sensitivity levels (MSL) under J-STD-020 standards.

Firmware requires the same unbundling discipline. Embedded modules with onboard microcontrollers, wireless SOCs, or FPGAs rely on firmware to configure registers, run state machines, and handle host communications over SPI, I2C, UART, or PCIe. Under bundled agreements, vendors deliver pre-compiled binaries or static libraries (.a /.lib formats).

Delivering only binaries hides security vulnerabilities, prevents low-power sleep optimizations, blocks RTOS task integration, and stops host developers from patching register-level bugs found in the field.

Unbundled firmware requires access to version-controlled source code in Git repositories. The repository needs to include all driver source files (.c /.h), register maps, interrupt service routines, linker scripts (.ld), build automation scripts (CMake / Makefiles), and exact compiler versions (GCC ARM Embedded, IAR Embedded Workbench, Keil MDK). Without the original build environment and configurations, raw source code alone cannot guarantee a reproducible binary that matches what was flashed at the factory.

Thermal management is another critical area where unbundling matters. High-power density modules like optical transceivers or motor drives dump significant heat through small surface areas. Bundled documentation usually offers just a junction-to-case thermal resistance value (Rth_jc) measured under ideal lab conditions.

Unbundled deliverables require native 3D STEP models with thermal boundary conditions, finite element analysis (FEA) grid files, and Touchstone S-parameter files (.s2p /.s4p) across operating temperatures (-40°C to +105°C). These models let hardware engineers simulate thermal conduction through PCB ground planes and heatsinks before committing to enclosure tooling.

Unbundling mechanical interface definitions ensures proper physical fit. Edge-castellated modules, surface-mount land grid arrays (LGA), and high-density connectors require tight tolerances. Unbundled packages include native mechanical drawings specifying solder mask expansion rules, stencil aperture geometry, pin coplanarity, and recommended IPC-7351 footprint guidelines.

Software drivers between the host processor and module coprocessors need to be unbundled down to register-level access. Proprietary host API wrappers often add overhead and block hardware acceleration features. Access to raw hardware abstraction layer (HAL) source code lets system designers integrate module register controls directly into DMA streams, cutting latency and power consumption during transfers.

Standard IPC-2581 output files carry full intelligent netlist data, removing single-vendor CAD dependencies while preserving complete fabrication geometry.

Component change notifications are a mandatory contractual deliverable in unbundled hardware packages. Vendors must commit to formal Part Change Notification (PCN) procedures conforming to JESD46 standards. This forces the supplier to give at least ninety days advance written notice before changing silicon revisions, substrate suppliers, passive component vendors, or encapsulation materials, giving the engineering team time to re-qualify the module before production.

Bench

Testing semicustom modules during mass production requires automated fixtures, test instrumentation, and custom software. In traditional bundled sourcing, vendors design, build, and maintain test jigs at their own facilities while billing the buyer for generic tooling. The buyer gets passing test reports but has zero visibility into test coverage, measurement limits, calibration algorithms, or fault detection logic.

When quality issues hit the assembly line, the buyer cannot tell whether failures stem from host integration errors, component drift, or weak factory screening.

Unbundling deliverables requires transferring factory test fixture designs and operational software in full. A working factory test setup relies on specialized hardware and software components built specifically for the customized module.

Establishing test fixture deliverables requires structured engineering procedures to validate that transferred test suites function independently of supplier personnel. Building a secondary, fully operational test station inside the buyer’s quality assurance facility validates the completeness of the transferred documentation package.

1. Receive mechanical CAD files, pogo-pin placement maps, wiring schematics, and the raw bill of materials for the test fixture.
2. Fabricate the mechanical fixture enclosure, install spring-loaded pogo pins into alignment plates, and wire signal lines to interface connectors according to the schematics.
3. Compile the automated test executive software from source code using the specified runtime environment and library dependencies.
4. Connect target instruments ~ including vector network analyzers, digital oscilloscopes, spectrum analyzers, and programmable power supplies ~ to the control host over GPIB or Ethernet.
5. Run self-test diagnostic routines on the assembled station using calibrated golden reference modules to establish baseline measurements.
6. Run a sample batch of uncalibrated prototype modules through the test sequence, confirming that trimming routines write valid calibration constants to onboard non-volatile memory.
7. Introduce intentional hardware faults into sacrificial test modules to verify that the automated test software correctly catches opens, shorts, out-of-spec power levels, and corrupted firmware.

Unbundling test executive software requires full access to test scripts, measurement limit databases, and instrument drivers. Vendors using closed, compiled test executives often hide loose tolerances to artificially boost factory yields. With unbundled test software, host engineers can inspect exact measurement algorithms, sweep times, averaging factors, and pass/fail windows.

Static limits hardcoded into binaries must be moved into editable configuration files (XML or JSON) backed by statistical process control (SPC) data showing Cpk capability metrics above 1.33 for critical parameters.

Calibration routines used during factory screening are another essential deliverable. Modern RF modules need individual per-unit calibration to compensate for component tolerances, amplifier non-linearities, and frequency variations. Trimming algorithms calculate offset values and write them into non-volatile memory during production testing.

An unbundled deliverable package includes uncompiled source code for these calibration algorithms, temperature compensation formulas, and precision requirements for reference instruments used on the line.

Boundary scan testing built on the IEEE 1149.1 JTAG standard is critical for catching defects. Fine-pitch Ball Grid Array (BGA) components and land grid array pads prevent visual inspection of solder joints beneath package bodies. Deliverables must include complete Boundary Scan Description Language (BSDL) files for all digital ICs, JTAG chain configurations, and test vector suites.

These BSDL assets let incoming inspection teams spot unsoldered pins, solder bridges, and damaged IC pads without tearing apart boards.

Measurement uncertainty analyses are another essential piece of the test package. A test result is only meaningful when paired with a calculated measurement uncertainty profile. Unbundled documentation requires suppliers to submit ISO/IEC 17025 compliant uncertainty budgets covering instrument errors, cable losses, fixture contact resistance, and thermal drift.

This baseline prevents disputes when incoming quality control at the buyer’s facility turns up failure rates that differ from factory gate reports.

Roughly sixty percent of custom test fixture transfer packages lack essential calibration coefficient source files. That omission leaves secondary test stations incapable of programming correct RF power tables into fresh modules.

Supplier excuses about retaining test fixture IP usually cite proprietary screening methods or confidential yield optimization. In practice, these claims often hide weak test coverage or relaxed screening limits. When a vendor refuses to supply unbundled test assets, the buyer loses the ability to audit production quality or move manufacturing if yields drop.

Custody

Clear ownership of intellectual property created during semicustom engineering prevents severe legal and operational deadlocks. Semicustom development sits in a grey area where vendor background IP merges with buyer-funded foreground IP. Background IP includes the supplier’s pre-existing module architecture, patented RF layout structures, standard firmware stacks, and base platform schematics.

Foreground IP covers all customizations, host-interface board modifications, specialized firmware extensions, custom pinouts, and integration artwork paid for under non-recurring engineering items.

Contracts must define these IP boundaries with absolute clarity. Without explicit contractual unbundling, suppliers routinely classify the entire customized design database as derivative background IP owned exclusively by the vendor. That leaves the buyer with zero rights to the customized schematics, layout, or firmware modifications despite paying for them.

The buyer must secure a perpetual, worldwide, non-exclusive, royalty-free license to use, modify, reproduce, and manufacture the custom engineering outputs, along with the right to sublicense those assets to secondary contract manufacturing partners.

Manufacturing transfer packages gather every physical, electrical, and software asset needed to build the module at an independent facility. A complete transfer package allows an alternate contract manufacturer to source components, fabricate boards, assemble surface-mount parts, flash firmware, and run functional calibrations without contacting the original developer.

Verifying design transfer packages requires strict adherence to international electronics manufacturing standards. The IPC-2581 standard provides an open, XML-based format for bare-board fabrication, assembly drawings, and test data exchange. Requiring IPC-2581 formatted data eliminates dependence on proprietary CAD file formats, ensuring long-term data readability across different manufacturing platforms.

• Fabrication data packages including IPC-2581 or ODB++ files, Gerber X2 artwork, NC drill files, layer stack-up definitions, and fabrication notes conforming to IPC-6012 Class 3 specifications.
• Assembly data sets comprising pick-and-place centroid files (X-Y coordinates, rotation, side), stencil aperture files (Gencad/Gerber), top/bottom component assembly drawings, and IPC-A-610 acceptability criteria specs.
• Direct component sourcing lists with unblinded bill of materials linking every reference designator to primary and secondary MPNs, distributor part numbers, packaging formats (tape-and-reel/tray), and component MSL ratings.
• Firmware binary creation tools including version-controlled repository archives, verified toolchain installer images, link scripts, chip configuration fuse settings, and automated build execution scripts.
• Production qualification records consisting of initial sample inspection reports (ISIR), design failure mode and effects analyses (DFMEA), process failure mode and effects analyses (PFMEA), and environmental test certificates.

Source code and design file escrow agreements offer critical risk mitigation when suppliers refuse immediate physical handover of native files. Under an escrow agreement, the vendor deposits updated native CAD databases, uncompiled firmware source code, toolchain installers, and test fixture designs with an independent escrow agent. The contract defines explicit release triggers, such as vendor insolvency, failure to deliver modules within agreed lead times, breach of quality agreements, or product discontinuation without a direct form, fit, and function replacement.

Escrow deposits require semi-annual compilation audits to verify that deposited source code builds cleanly into functional binary images matching factory hardware.

Qualifying a secondary manufacturing source using an unbundled transfer package is the ultimate test of technical custody. A transfer package remains a theoretical asset until an independent assembly plant builds, tests, and certifies a pilot batch of modules without help from the original vendor. Dual-sourcing qualification audits evaluate PCB fab yield, pick-and-place efficiency, reflow solder defect rates (measured in DPMO – Defects Per Million Opportunities), firmware flashing reliability, and test station correlation.

Which Design Transfer Rights Survive Contract Termination?

Contracts governing semicustom developments must explicitly define which rights survive contract termination. Standard vendor terms often state that upon termination, all rights to produce customized module variants revert to the supplier, blocking the buyer from using secondary manufacturing options. The agreement must protect the buyer’s perpetual right to manufacture, service, and update the custom hardware regardless of why the contract ended, provided all valid NRE invoices were paid during development.

Escrow release mechanisms often fail during corporate restructurings because contract language defines bankruptcy triggers too narrowly. Setting operational failure metrics ~ such as three consecutive months of missed delivery schedules or uncorrected defect rates exceeding two percent ~ creates practical release triggers long before formal insolvency proceedings begin. Making sure the escrow package contains fully documented build environments ensures the engineering team can use released assets immediately.

Resolving ownership disputes over derivative IP comes down to analyzing the precise scope of work. If a buyer pays for custom firmware to modify host communication protocols, that interface code belongs entirely to the buyer as foreground IP. When suppliers try to claim ownership of host interface modifications, the buyer faces expensive licensing demands when migrating to next-generation silicon platforms.

Explicitly defining host-side interfaces and custom application code as buyer foreground IP prevents post-development commercial hold-ups.

Unbundled engineering agreements must include formal audits of deposited assets. Third-party auditors build physical boards from deposited fabrication data, compile firmware from deposited repository branches, and test the compiled binaries on actual hardware. Identifying missing linker scripts, footprint errors, or broken code dependencies during an audit prevents disastrous delays when emergency manufacturing transfers become necessary.

The operational question remains: how do buyers prevent module vendors from quietly introducing proprietary, un-escrowed silicon revisions into module substrates midway through a multi-year production contract?

Valuation

Pricing semicustom engineering work requires evaluating two competing financial structures: bundled NRE with elevated unit hardware costs versus unbundled NRE with raw landed component pricing. Suppliers routinely promote bundled development models by quoting artificially low initial NRE fees, often framing custom work as a complimentary service. In exchange, the supplier embeds their real development costs, capital risks, and profit margins into per-unit hardware prices across the module’s expected production run.

This distorts production economics, penalizes scaling to high volumes, and conceals true manufacturing costs.

Unbundled engineering valuation requires explicit itemization of NRE fees based on fully burdened hourly rates. The engineering disciplines involved in semicustom development carry distinct market rates depending on technical specialization.

Unbundling engineering scope alters the total cost of ownership trajectory as production volumes grow. Calculating the break-even volume between bundled and unbundled sourcing strategies relies on simple landed-cost arithmetic. A bundled procurement model charges a nominal NRE fee (NRE_b) alongside an inflated per-unit module cost (P_b).

An unbundled model charges a higher upfront engineering fee (NRE_u) reflecting true development costs and complete asset transfer, paired with a bare component unit price (P_u) mirroring actual bill-of-materials costs plus a transparent manufacturing markup (typically 12% to 18%).

The total cost equation for bundled sourcing maps as:

Total_Cost_Bundled = NRE_b + (P_b Volume)

The total cost equation for unbundled sourcing maps as:

Total_Cost_Unbundled = NRE_u + (P_u Volume)

The economic crossover point (Break-Even Volume) where unbundled sourcing yields absolute savings is calculated by setting the total cost equations equal:

Break_Even_Volume = (NRE_u – NRE_b) / (P_b – P_u)

Consider a practical hardware program sourcing a customized Bluetooth Low Energy / Ultra-Wideband (BLE/UWB) combo module. The supplier offers two commercial options for a 50,000-unit production run:

Option A (Bundled): Upfront NRE fee of $15,000 with a per-unit module price of $14.50. Design deliverables remain proprietary to the vendor; no source code or native CAD files are transferred.

Option B (Unbundled): Upfront NRE fee of $65,000 providing full native CAD deliverables, firmware repositories, test fixture designs, and second-sourcing manufacturing rights. The unbundled per-unit module price drops to $9.20 based on unblinded BOM costs plus an 15% assembly margin.

Applying the break-even calculation:

Break_Even_Volume = ($65,000 – $15,000) / ($14.50 – $9.20)

Break_Even_Volume = $50,000 / $5.30 = 9,434 units

At 50,000 units, Option A costs $740,000 ($15,000 + $725,000). Option B costs $525,000 ($65,000 + $460,000). Mandating unbundled deliverables saves $215,000 on the initial production run while securing complete technical custody of the hardware and firmware intellectual property.

The initial $50,000 premium paid for unbundled engineering deliverables pays for itself within the first 9,434 units shipped.

Unbundled engineering deliverables yield net savings once production volume crosses the break-even threshold defined by the unbundled unit margin spread.

Unbundled contracts force rigorous verification of invoiced engineering hours. NRE proposals must link payment milestones directly to the delivery and audit of verified deliverables rather than calendar dates. A standard milestone schedule allocates 20% upon schematic capture sign-off, 30% upon physical layout and stack-up review, 30% upon functional prototype delivery with native source code, and the final 20% upon delivery and verification of the complete manufacturing transfer and test package.

Holding back final NRE payments until test jigs and build packages pass correlation audits protects buyers from incomplete deliveries. Suppliers working under fixed-price NRE contracts often try to skip documentation once prototype hardware works. Structuring contracts so that twenty percent of engineering fees depend on incoming test verification ensures the vendor finishes layout cleanup, file formatting, repository commits, and user documentation.

Valuing unbundled deliverables also means accounting for host-side tooling and qualification expenses. Second-sourcing a module with transferred manufacturing packages requires funding secondary PCB tooling, surface-mount stencils, automated optical inspection (AOI) programming, and factory pilot runs. These setup costs typically range from $5,000 to $15,000 per manufacturing line.

Factoring setup fees into the initial financial model gives a complete picture of total landed manufacturing costs.

Long-term maintenance costs drop under unbundled engineering structures. When host applications demand minor changes ~ such as remapping an I2C pin to an SPI bus or updating an internal LDO regulator to improve power efficiency ~ an in-house engineer with native CAD assets can execute the modification in twenty hours. Asking the original vendor to make that same modification under a bundled agreement routinely results in change orders exceeding two hundred engineering hours, plus long delays.

Pay for engineering deliverables once as itemized NRE assets, or pay forever inside every shipped module’s margin.