Trap Rich Layer Physics for RF Silicon Substrates
Trap-rich polysilicon layers beneath buried oxide pin interface carriers to eliminate parasitic conduction and lower sub-6 GHz harmonic generation.
Silicon Substrate Surface Conduction Mitigation in High Resistivity RF Transceivers
Trap-rich polysilicon layers suppress parasitic surface conduction in high-resistivity silicon transceivers, lowering second harmonics below -85 dBc at +25 dBm RF input.
Modeling Long Term Time Dependent Dielectric Breakdown Acceleration in Trap Rich High Resistivity Silicon Wafer Substrates
Dielectric breakdown modeling on trap rich silicon requires temperature adjusted voltage acceleration factors to prevent early RF switch gate oxide failure.
Silicon Substrate Surface Conduction and Dielectric Passivation Fundamentals
Trap-rich polysilicon passivation pins interface charges on high-resistivity silicon, suppressing surface conduction and harmonic spur spikes across RF switches.
Silicon Wafer Processing and Substrate Dielectric Degradation Mechanisms
Substrate dielectric degradation reduces RF transceiver link budgets over time, requiring a minimum four-decibel margin allowance during module procurement.